The present invention relates to an integrated circuit and a testing method for an integrated circuit.
FIG. 2 shows the entire configuration of a conventional integrated circuit. In FIG. 2, a reference numeral 14 denotes a CPU and a reference numeral 13 denotes an integrated circuit, which includes an address decoder 10, a first logic circuit 11 and a second logic circuit 12 having the same function as the first logic circuit 11.
The first logic circuit 11 has one or more logic functions and includes a register 11a to which an arbitrary address is previously allocated, so that it can work as an adder when the value stored in the register 11a is “0” and work as a subtracter when the value is “1”. When an address signal s200a corresponding to the register 11a is output from the CPU 14, the address decoder 10 decodes the address signal s200a so as to output a first address select signal (enable signal) s11 to the register 11a. The register 11a receives a data signal s200b output from the CPU 14 and is set to the value of the data signal s200b, so that the first logic circuit 11 can perform the operation defined by the register 11a and output the result to a signal line s11a. The first logic circuit 11 can be tested by monitoring the value of this output on the signal line s11a. 
Similarly, the second logic circuit 12 has the same function as the first logic circuit 11, and includes a register 12a to which an arbitrary address different from that of the register 11a of the first logic circuit 11 is previously allocated, so that the second logic circuit 12 can work as an adder when the value stored in the register 12a is “0” and work as a subtracter when the value is “1”. When the CPU 14 outputs an address signal s200a corresponding to the register 12a, the address decoder 10 decodes the address signal s200a so as to output an address select signal (enable signal) s12 to the register 12a. The register 12a of the second logic circuit 12 is set to the value of a data signal s200b output from the CPU 14. The second logic circuit 12 performs the operation defined by the register 12a and outputs the result to a signal line s12a. The second logic circuit 2 can be tested by monitoring the value of this output on the signal line s12a. 
In this manner, in the conventional testing method, all logic circuits included in an integrated circuit to be tested are made to perform a normal operation repeatedly one by one so as to monitor the output values of the respective logic circuits.
Recently, in accordance with the increased degree of integration of LSIs, a logic circuit is used as a highly general-purpose IP (intellectual property) in fabrication of an LSI in order to improve the design efficiency.
However, when an integrated circuit including a plurality of logic circuits having the same function as in the aforementioned conventional integrated circuit is tested, it is necessary to successively test the respective logic circuits one by one, which disadvantageously requires a long time for the testing.
Furthermore, when a configuration for enabling simultaneous testing of a plurality of logic circuits is employed, there arises a problem that a large number of test pins are necessary for externally monitoring output signals of the respective logic circuits.